Field Programmable Gate Array Implem Ri
نویسندگان
چکیده
We present an 8-bit field programmable gate arr (FPGA) implementation of 128-bit block and 128-bit k Advanced Encryption Standard (AES) Rijndael. The 8Rijndael encryption data path operates at 13.7MHz a consumes 226 clock cycles resulting in a throughput of 7.8 bits per second. The Rijndael decryption data path operates 8.8MHz and consumes 226 clock cycles resulting in throughput of 5 M bits per second.
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